1. Field of the Invention
The present invention relates to a packet communication device for performing routing and forwarding of layer 2 frames such as the Ethernet (registered commercial trademark), layer 3 packets for example, IP (Internet Protocol) and even upper layer data packets.
2. Description of Related Art    [Non-patent document 1] Hitachi Review Vol. 49 (2000), No. 4    [Non-patent document 2] U.S. Pat. No. 6,905,725    [Patent document 1] JP-A No. 64542/2002
Data traffic including traffic on the Internet has rapidly increased in recent years. A shift can also be observed towards an Internet infrastructure with high quality and highly reliable service, which has been performed on leased lines. To cope with this shift, packet communication devices as well as transmission paths must offer high speed operation, be highly reliable and have a large capacity. Packet communication devices must also be flexible in terms of functions in order to be able to respond swiftly with new routing protocols and new services or to be capable of easily adding these functions when needed. The router is one example of a packet communications device for layer 3 processing. There are also many special function routing devices in particular whose hardware performs high speed routing and forwarding. A structure for a hardware router is disclosed for example in non-patent document 1 and non-patent document 2. FIG. 2 is a block diagram of the hardware router disclosed in the non-patent document. Multiple routing processors 801 containing a network interface 811 are mutually connected by a crossbar switch 800. Each routing processor 801 is composed of a forwarding controller 812, a routing controller 813, a routing table 814 and a packet buffer 815. The packet header of the IP packets input through the network interface 811 are extracted from the packet by the forwarding controller 812, and a route search performed by the routing controller 813. Destination information, filtering information for security purposes, and QoS (Quality of Service) information are entered in the routing table 814. The IP packet is input to the packet buffer 815 after search processing is completed. Then, the packet is sent to the desired output port through the crossbar switch 800. The routing manager 802 contains a routing protocol and exchanges routing information with neighbor routers. This routing manager 802 also establishes the forwarding path for each IP packet. This established forwarding path is reflected in the routing table 814 within the routing processor 801. In this way, this router has a structure with distributed routing processors and packet buffer sections.
An example of another hardware router structure is disclosed in U.S. Pat. No. 6,905,725 (Non-patent document 2).
FIG. 3 is a block diagram showing the hardware router disclosed in non-patent document 2. The IP packet input through an input port 901 is stored in a buffer memory 903 through an input switch 902. In the input switch 902, key information 904, which is extracted from the IP packet such as the destination IP address, is input to a controller 905. After the destination search is performed for each packet in the controller 905, that result (Result 906) is sent to an output switch 907. Based on this result 906, the output switch 907 then loads the IP packets accumulated in the buffer memory 903 into the corresponding output port 908. The routing processor (controller 905) and the packet buffer in this way constitute a centralized structure.
In the technology disclosed in JP-A No. 64542/2002 (patent document 1), the labeled packets and IP packets are separated based on header information attached to them on an input line interface. The IP header was then sent to a forwarding engine after separation. However, no consideration was given to scalability in this method.
The switch disclosed in non-technical document 1 has high scalability performance since the routing functions and forwarding functions are distributed. In the structure shown in non-patent document 1 however, the forward controller is tightly coupled to the routing controller and installed in the same routing processor section. From the viewpoint of hardware implementation, the hardware have to be completely redesigned to introduce new routing protocols and new services. In other words, this structure is not suitable for adding new functions.
The switch architecture disclosed in non-patent document 2 has centralized control of routing and forwarding functions. Therefore, buffer memory usage is highly efficient and the device can be compactly fabricated. However, it is difficult to apply this architecture for a large scale router because of processing bottlenecks of centralized routing functions and forwarding functions. In terms of flexibility for adding new functions, the routing hardware would require complete redesigning for new protocols, even though the routing functions and forwarding functions have been distributed. Besides, this structure is not able to perform services with upper layer packets.